1. Field of the Invention
The present invention relates to microelectronic circuits, and more particularly to a structure and method to control leakage current in subunit microelectronic circuits.
2. Description of the Related Art
Power consumption due to leakage current is increasing rapidly in modern very large scale integration (VLSI) design and is becoming a significant problem in not only meeting the thermal envelope in high performance designs, but also meeting power dissipation constraints in low-power portable devices.
Conventional designs require a control signal that activates or deactivates leakage reduction logic. This is typically performed at chip level; for example, a processor goes into sleep mode. One long-standing problem includes leakage at the subunit level, which is typically not controlled (in both hardware and for predictive method techniques), for example, in microprocessors and memories, such as at pipeline stages, or portions of pipeline stages.
Therefore, a need exists for a system and method for controlling leakage at the subunit level in electronic circuits.